Adder Networks

Motivation

A computer ultimately adds integers bit by bit in hardware. Even adding two 4-bit numbers raises the central question of digital logic: how is the carry passed from one bit position to the next? Different adder networks answer this with different trade-offs between circuit area, number of clock cycles and propagation delay. This tool contrasts three classic variants — the von Neumann adder, the parallel adder and the serial adder — and shows for each the bit/decimal step table together with the carry/overflow bit $u$.

All three compute the same sum

with $a, p \in \{0, \dots, 15\}$. The result may leave the 4-bit range: if $a + p \ge 16$ an overflow occurs, captured in the fifth bit $u = \lfloor (a+p)/16 \rfloor$. The accumulator then holds $(a + p) \bmod 16$, and the full value is $u \cdot 16 + \text{acc}$.

How the three networks work

von Neumann adder

The von Neumann adder separates sum without carry from carry and iterates until no carry remains. At each step, for the current accumulator $a$ and buffer $p$:

Here $\oplus$ is bitwise XOR (the carry-free sum) and $(a \wedge p) \ll 1$ shifts the carries generated at each position one place to the left. As soon as a carry reaches bit position $4$, the overflow bit is set:

The iteration ends when $p = 0$ (the $s$ column then becomes $0$). The number of steps depends on how far the carries propagate.

parallel adder

The parallel adder forms the sum in one combinational step (a ripple-carry chain, shown here as a single cycle). The lower four bits land in the accumulator, the fifth bit is the carry-out:

It needs the fewest cycles but the most simultaneous logic.

serial adder

The serial adder uses one full adder that processes one bit per clock — starting from the least-significant bit (LSB) upward. For the current bits $a_0, p_0$ and the carry $u$, the full-adder equations are

The sum bit $s_0$ is shifted into the most-significant bit of the accumulator, while $a$ and $p$ shift right by one. After four cycles the accumulator holds the sum and $u$ is the carry-out. The serial adder needs the least logic but four clock cycles.

Worked example

We add $a = 9 = 1001_2$ and $p = 6 = 0110_2$ with the von Neumann adder — the preset of the calculator above.

Since $a \wedge p = 0$ there is no carry: after a single step the buffer is already $0$, the overflow bit stays $u = 0$, and the accumulator holds $1111_2 = 15$. Indeed $9 + 6 = 15 < 16$, so it just fits into four bits.

Common pitfalls

• Reading the accumulator without the carry: the accumulator only holds $(a + p) \bmod 16$. On overflow you must add bit $u$ as the $16$s place, or the carry is missing from the final result.
• Confusing XOR with addition: in the von Neumann step $a \oplus p$ is the carry-free sum — not $a + p$. The carry lives separately in $(a \wedge p) \ll 1$.
• Wrong bit order in the serial adder: it starts at the LSB and shifts right. Starting at the MSB propagates the carry in the wrong direction.
• Forgetting the carry $u$ between cycles: the serial adder carries $u$ from cycle to cycle; only then does a correct multi-bit addition emerge.